MAX152EPP+【PDF 12/12 页】IC ADC 8BIT 1UA PWR-DWN 20-DIP

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Sheet目录2009

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____________Analog Considerations

Reference

Figures 7a-7c show some reference connections.

VREF+ and VREF- inputs set the full-scale and zero-

input voltages of the ADC. The voltage at VREF-

defines the input that produces an output code of all

zeros, and the voltage at VREF+ defines the input that

produces an output code of all ones.

The internal resistance from VREF+ to VREF- may be as

low as 1k

, and current will flow through it even when

the MAX152 is shut down. Figure 7d shows how an N-

channel MOSFET may be connected to VREF- to break

this path during power-down. The FET should have an

on resistance < 2

with a 3V gate drive.

Although VREF+ is frequently connected to VDD, this

circuit uses a low current, low-dropout, 2.5V voltage

reference – the MAX872. Since the MAX872 cannot

continuously furnish enough current for the reference

resistance, this circuit is intended for applications where

the MAX152 is normally in standby and is turned on in

order to make measurements at intervals greater than

20s. The capacitor C1 connected to VREF+ is slowly

charged by the MAX872 during the standby period and

furnishes the reference current during the short measure-

ment period.

The 2.2F value of C1 is chosen so that its voltage drops

by less than 1/2LSB during the conversion process.

Larger capacitors reduce the error still further. Use

ceramic or tantalum capacitors for C1.

When VREF- is switched, as in Figure 7d, a new conver-

sion can be initiated after waiting a time equal to the

power-up delay (tUP) plus the turn-on time of the N-chan-

nel FET.

Bypassing

A 4.7F electrolytic in parallel with a 0.1F ceramic

capacitor should be used to bypass VDD to GND.

These capacitors should have minimal lead length.

The reference inputs should be bypassed with 0.1F

capacitors, as shown in Figures 7a-7c.

Input Current

Figure 8 shows the equivalent circuit of the converter

input. When the conversion starts and

WR is low, VIN is

connected to sixteen 0.6pF capacitors. During this acqui-

sition phase, the input capacitors charge to the input volt-

age through the resistance of the internal analog switches.

In addition, about 12pF of stray capacitance must be

charged. The input can be modeled as an equivalent RC

network (Figure 9). As source impedance increases, the

capacitors take longer to charge.

The typical 22pF input capacitance allows source resis-

tance as high as 2.2k

without setup problems. For larg-

er resistances, the acquisition time (tP) must be increased.

MAX152

+3V, 8-Bit ADC with 1A Power-Down

_______________________________________________________________________________________

RON

RIN

VIN

MAX152

Figure 8. Equivalent Input Circuit

VIN

12pF

VIN

MAX152

10pF

Figure 9. RC Network Equivalent Input Model

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